1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming a semiconductor device, and more particularly to a method of forming a semiconductor memory, including a flash memory, and scaling of a memory using a common substrate structure, and to the structure resulting from the inventive method, including a floating gate on a back-plane.
2. Description of the Related Art
Non-volatile electrically erasable and programmable memory structures (EEPROMs), such as a flash memory, utilize a floating gate whose charging is controlled by appropriate biasing of the source, drain and controlling gate. A flash memory is unique in providing fast compact storage which is both nonvolatile and rewritable.
In a flash memory, the threshold voltage Vt for conduction of a field-effect transistor (FET) changes state depending upon the amount of charge stored in a floating gate (FG) part of the FET. The floating gate is a charge storing region which is isolated from a more traditional control gate (CG) (connected by xe2x80x9cwordlinexe2x80x9d) by a dielectric commonly based on silicon dioxide. The state of the Vt changes with the amount of charge stored by the FG.
The gate stack in such structures includes the silicon channel with an injection/tunneling oxide, the floating gate and a thicker control oxide with a controlling gate on top. They are usually designed for flash erase in a block, for writing by word, and derive a density advantage from their single transistor (element) structure.
Use of floating gates in memories have their origin in the earlier work of Kahng (e.g., see D. Kahng et al., xe2x80x9cA Floating Gate and its Application to Memory Devices,xe2x80x9d Bell Systems Technical Journal, 46 1288 (1967)) who described a non-volatile MOS memory with a conducting metal layer interposed between the gate and the channel with oxide as a separating layer. This structure used tunneling, direct and indirect, without the use of hot carriers. The ideas behind this structure evolved to use of dielectrics in MNOS cells (e.g., See H. A. R. Wagener et al., xe2x80x9cThe Variable Threshold Transistor, A New Electrically Alterable Non-Destructive Read-Only Storage Device,xe2x80x9d Tech. Dig. of IEDM, Washington D.C. (1987)), use of hot carriers to inject into floating gate structures (e.g., see D. Frohmann-Bentchkowsky, xe2x80x9cA Fully Decoded 2048-bit Electrically Programmable MOS-ROMxe2x80x9d Tech. Dig. of ISSCC, 80 (1971)) and the more write-efficient structures with an external gate whose various forms are used today (e.g., see Iizuka et al., xe2x80x9cStacked Gate Avalanche Injection Type MOS (SAMOS) Memoryxe2x80x9d, Tech. Dig. of 4th Conf. Sol. St. Dev., Tokyo (1972) and Japan J. of Appl. Phys., 42 158 (1973)).
These forms of electrically erasable and programmable memories include structures such as flash structures using NAND and NOR architectures. Most of these structures use various hot carrier injection processes.
FIGS. 1(A)-1(C) illustrate some different types of structures which such non-volatile memories may adopt, such as a floating gate with oxide injection (FLOTOX) using injection from the drain, erasable tunneling oxide (ETOX) using injection from the channel, and, source side injection (SISOS) using injection from the source using a field from a select gate. Being a single element structure, these structures have advantages in packing, and they have specific forms of unipolar or bipolar write, erase, and read cycles that are compatible with non-volatile operation.
However, only one form (e.g., the nano-crystal memory, as disclosed in U.S. Pat. Nos. 5,508,543 and 5,714,766, commonly assigned with the present application and incorporated herein by reference) may use direct tunneling with non-volatility. An example of this structure is shown in FIG. 1(D).
A further problem arises in that, as device sizes shrink, it becomes increasingly difficult to make these memory structures since the injection oxide and the control oxide cannot be shrunk because of charge leakage. This non-scalability of oxide thickness results in a larger (e.g., longer) electrical distance between the controlling gate and the channel than the gate length. The larger electrical distance makes integration and higher density more difficult, if not impossible. Additional consequences include read disturbance, poor transconductance and poor sub-threshold characteristics, and limited cyclability.
Moreover, an essential requirement of scaling of all field-effect-based structures is that all electrical distances must be scaled together simultaneously. In flash memory structures where the vertical stack has a physical thickness exceeding 47 nm (e.g., currently limited by the injection oxide thickness (greater than 7 nm), floating gate thickness (greater than 30 nm), and the control gate thickness (greater than 10 nm)), a constraint is placed on both minimum device size and voltages and power at which the devices are operable.
In view of the foregoing and other problems of the conventional systems and methods, it is an object of the present invention to provide a floating gate memory structure compatible with advanced devices that utilize a buried floating gate derived from a back-plane.
Another object is to provide a method for producing a compact, highly integrated structure which is nonvolatile.
Yet another object is to provide a method for providing a structure with a sufficiently small floating gate that limits the number of electrons stored and hence power dissipation.
In a first aspect of the present invention, a semiconductor memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate comprising a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.
In a second aspect of the present invention, a backplane transistor, includes: a first gate having an oxide and a channel, forming a transistor; and a back-plane, formed opposite to the channel, forming a floating gate region for storing different states of memory and including an oxide, the back-plane being isolated to function as a floating gate, wherein a thickness of the oxide of the floating gate is separately scalable from a thickness of the oxide of the first gate of the transistor.
In a third aspect, a memory, includes a buried floating gate, and a top gate having an oxide, thereby forming a transistor having a transistor channel, wherein leakage from the floating gate is decoupled through an injection oxide from that of controlling a transistor channel of the memory, wherein the floating gate is formed from a back-plane, thereby allowing the top gate and the oxide of the top gate to be scalable according to a size of the memory.
In a fourth aspect of the present invention, a memory system, including a back-plane, includes a transistor including a control gate and a transistor channel, and a floating gate opposite to the control gate and beneath the transistor channel, the floating gate being a back-gate formed on the back-plane.
In a fifth aspect of the invention, a method of producing a floating gate on the back of a transistor channel, includes steps of: forming a buried oxide on a conducting substrate; forming a back-plane over the buried oxide; forming a back oxide over the back-plane; and forming a silicon layer over the back oxide, the silicon layer having a comparable thickness to that of the back-plane, through which charge gets injected into the back-plane.
In the invention, a floating gate, including either a semiconductor or a metal, is buried under a thin transistor channel. Charge on the floating gate determines the threshold voltage of the device. The transistor""s conduction state can be read through a bias voltage at source, drain and the gate, thus describing the stored state of the device. The injection oxide for the buried floating gate can be made larger (e.g., approximately within a range of 7-10 nm) while the oxide for the top gate can be scaled to smaller dimensions.
By decoupling the oxide thickness of a floating gate from the scaling of the transistor, a device is achieved that can be scaled to significantly smaller dimensions than the conventional memory structures.
Further, by allowing for a large coupling capacitance between the floating gate and the channel and doped region, it allows for efficient transfer of electrons, without affecting the ability to sense the transistor conduction using the top gate.
Thus, the present invention describes a structure (and method)where the floating gate is decoupled, and is placed on the back of the conducting channel, thus allowing the top gate to be placed closer to the channel, and thereby resulting in stronger electrical control during a read operation.
By decoupling reading from charging and discharging, the structure of the present invention is more immune to read disturbances. Further, by providing for a very small floating gate region, the present invention provides for discrete electron sensitivity and low power consumption. Hence, a structure with a sufficiently small floating gate is provided which limits the number of electrons stored and hence power dissipation by having a capacitance in a small area which can store discrete electrons.
Additionally, by providing for a scaled control gate, the present invention allows for superior transistor characteristics, such as, for example, in leakage and transconductance, than in conventional memories (e.g., flash memories).